ESD protection devices and methods for forming ESD protection devices

ABSTRACT

The present disclosure provides a circuit that has a Radio Frequency (RF) input, an inductor between the RF input and with RF front end circuitry, a first diode coupled to the RF input and the inductor and with a power line, and a second diode coupled to the RF input and the inductor and with a complimentary power line.

CROSS-REFERENCE

The present disclosure is related to the following commonly assignedU.S. Patent Applications, their entire disclosures which areincorporated herein by reference: U.S. patent application Ser. No.12/985,948 filed Jan. 6, 2011, entitled, “ESD Protection Devices andMethods For Forming ESD Protection Devices” and U.S. patent applicationSer. No. 12/986,450 filed Jan. 7, 2011, entitled, “ESD ProtectionDevices and Methods For Forming ESD Protection Devices”.

TECHNICAL FIELD

The present disclosure relates to methods of fabricating electronicdevices, and more particularly, to electrostatic discharge (ESD)protection devices and methods for forming ESD protection devices.

BACKGROUND

The semiconductor integrated circuit (IC) industry has experienced rapidgrowth. Technological advances in IC materials and design have producedgenerations of ICs where each generation has smaller and more complexcircuits than the previous generation. These circuits may be sensitiveto electrostatic discharge (ESD) currents. Thus, ESD protection devicesare utilized to prevent and reduce damages to an IC caused by ESDcurrents. Traditionally, some ESD protection devices have parasiticcapacitance that is large enough to noticeably degrade Radio Frequency(RF) performance in the circuit being protected.

Therefore, while existing ESD protection devices have been generallyadequate for their intended purposes, they have not been entirelysatisfactory in every aspect.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the followingdetailed description when read with the accompanying figures. It isemphasized that, in accordance with the standard practice in theindustry, various features are not drawn to scale. In fact, thedimensions of the various features may be arbitrarily increased orreduced for clarity of discussion.

FIG. 1 is a block diagram illustration of an exemplary device, adaptedaccording to one embodiment;

FIG. 2 shows response time (partly dependent upon clamping speed) andovershoot (OS) in an exemplary scenario;

FIG. 3A is a cross-sectional illustration of exemplary device 300,adapted according to one embodiment;

FIG. 3B is a top-down view of device 300 with a marker indicating thecut for the cross-section of FIG. 3A; and

FIG. 4A is a cross-sectional illustration of an exemplary strip-type,N-type poly-bounded diode, adapted according to one embodiment;

FIG. 4B is a top-down view of the diode of FIG. 4A;

FIG. 5 is a top-down illustration of an exemplary polygon-shapedpoly-bounded diode;

FIG. 6 is an illustration of exemplary embodiments including a hexagonalpoly-bounded diode and an octagonal poly-bounded diode;

FIG. 7 is a flowchart of an exemplary method for fabricating a device,adapted according to one embodiment;

FIG. 8 shows one example circuit in which polygonal gated diodes can beused;

FIG. 9 is an illustration of an exemplary circuit adapted according toone embodiment.

FIG. 10 is an illustration of the circuit of FIG. 9 showing the currentpaths during an ESD event when ESD diodes are forward biased;

FIG. 11 shows an alternate embodiment circuit with a differentarchitecture than the embodiment shown in FIGS. 9 and 10;

FIG. 12 is an illustration of an exemplary method adapted according toone embodiment for fabricating a circuit;

FIG. 13 is an illustration of an exemplary circuit, adapted according toone embodiment;

FIG. 14 is an illustration of an exemplary matching circuit, adaptedaccording to one embodiment;

FIG. 15 is an illustration of an exemplary matching circuit, adaptedaccording to one embodiment;

FIG. 16 is an illustration of an exemplary matching circuit, adaptedaccording to one embodiment;

FIG. 17 is an illustration of an exemplary matching circuit, adaptedaccording to one embodiment;

FIG. 18 is an illustration of an exemplary matching circuit, adaptedaccording to one embodiment;

FIG. 19 is an illustration of an exemplary matching circuit, adaptedaccording to one embodiment;

FIGS. 20 and 21 provide variations on the embodiment shown in FIG. 15,where a transformer is used for impedance matching and ESD currentbypass; and

FIG. 22 is an illustration of an exemplary method for fabricating adevice according to one embodiment.

SUMMARY

The present disclosure provides many embodiments. One embodiment of thepresent disclosure involves a circuit that has a Radio Frequency (RF)input pad, an inductor between the RF input pad and with the RF frontend circuitry, a first diode coupled to the RF input pad and to theinductor and to the power line, and a second diode coupled to the RFinput and to the inductor and to a complimentary power line. The firstand second diodes are reverse biased during normal operation of the RFfront end circuitry. The first and second diodes provide respectivefirst and second electrostatic discharge (ESD) current paths away fromthe RF front-end circuitry during an ESD event.

Another embodiment of the present disclosure involves a circuit that hasa RF input coupled to RF front end circuitry, an inductor between the RFinput and the RF front end circuitry, and a first diode and a seconddiode between the RF input and the RF front end circuitry. The firstdiode is arranged to provide a first ESD current path between the RFinput and a power line, and the second diode is arranged to provide asecond ESD current path between the RF input and a complimentary powerline.

Still another embodiment of the present disclosure involves a method offabricating a circuit. The method includes coupling a RF input with RFfront end circuitry, disposing a first and a second diode in the circuitso that the first and second diodes are coupled to the RF input and theRF front end circuitry. The first and second diodes are both arrangedwith a forward direction from a complimentary power line to a powerline. The method also includes disposing an inductor in the circuit sothat the inductor is coupled to the first and second diodes and isbetween the RF input and the RF front end circuitry.

DETAILED DESCRIPTION

It is understood that the following disclosure provides many differentembodiments, or examples, for implementing different features of variousembodiments. Specific examples of components and arrangements aredescribed below to simplify the present disclosure. These are, ofcourse, merely examples and are not intended to be limiting. Forexample, the formation of a first feature over or on a second feature inthe description that follows may include embodiments in which the firstand second features are formed in direct contact, and may also includeembodiments in which additional features may be formed between the firstand second features, such that the first and second features may not bein direct contact. In addition, the present disclosure may repeatreference numerals and/or letters in the various examples. Thisrepetition is for the purpose of simplicity and clarity and does not initself dictate a relationship between the various embodiments and/orconfigurations discussed.

As technology progresses, semiconductor devices are generally beingscaled down. As semiconductor devices get smaller, gate oxide breakdownvoltages may become lower due to thinner gate oxide layers and ESDprotection becomes more important. However, at high frequencies, someESD protection devices may provide excessive parasitic capacitance andinterfere with impedance matching networks. Various embodiments of thisdisclosure provide better performance, as explained in more detailbelow.

FIG. 1 is a block diagram illustration of an exemplary device 100,adapted according to one embodiment. Device 100 provides an illustrationof a generalized configuration of various embodiments disclosed hereinbelow. For instance, device 100 is a circuit that includes ESDprotection device 101 positioned between Vdd 104 and ground (e.g., Vss)106. ESD protection device 101 works in conjunction with clamp 103 toprotect Radio Frequency (RF) circuit 102 from damaging effects of ESD atI/O terminal 105. In one example scenario, ESD protection device 101limits the magnitude of an ESD pulse somewhat while directing thecurrent from the ESD pulse to clamp 103, where clamp 103 quickly reducesthe voltage of the ESD pulse to an acceptable range.

ESD protection device 101 includes some amount of parasitic capacitance,shown in FIG. 1 as C_(esd). The effect of C_(esd) on a given devicedepends on the particular characteristics of a given device, suchcharacteristics including, for example, operating frequency and inputimpedance. Various embodiments described herein provide for techniquesto minimize C_(esd) and/or to utilize C_(esd) in impedance matching.Various embodiments may also decrease overshoot voltage for a given ESDevent, thereby allowing faster and more effective clamping of the ESDevent. FIG. 2 shows response time (partly dependent upon clamping speed)and overshoot (OS) in an exemplary scenario. The particular values shownin FIG. 2 are for conceptual illustration only and may or may notdirectly apply to any of the various embodiments shown herein.

Returning to FIG. 1, ESD protection device 101 is shown having twocomponents 110, 111 for ease of illustration, and it is understood thatESD protection device 101 may be implemented with one or more circuitcomponents. Furthermore, device 100 is shown as an RF circuit, thoughthe scope of embodiments is not limited to any particular frequencyrange or application. For instance, some embodiments may be applied todevices that operate in the millimeter wave range or other frequencyrange. Various embodiments can be implemented in configurations similarto that shown in FIG. 1. For example, one or both of components 110, 111can use protection devices as discussed below in FIGS. 3A-6.

FIG. 3A is a cross-sectional illustration of exemplary device 300,adapted according to one embodiment. FIG. 3B is a top-down view ofdevice 300 with a marker indicating the cut for the cross-section ofFIG. 3A. Device 300 is strip-type, P-type poly-bounded diode. Device 300is built on P-substrate 301 with various doped regions 302-309 thereon.Device 300 also includes polysilicon (poly) layers 312, 314 andinput/output terminals 315-317. In use, anode 317 is an RF input, andcathodes 315, 316 are in communication with Vdd.

FIG. 4A is a cross-sectional illustration of exemplary strip-type,N-type poly-bounded diode 400, adapted according to one embodiment. FIG.4B is a top-down view of diode 400. Diode 400 is built on P-typesubstrate 401 with doped regions 402-405 thereon. Diode 400 includespoly layers 412, 414 and input/output terminals 415-417. Cathode 417 canbe used as an RF input, and anodes 415, 416 can be in communication withVss or other ground.

Some devices using poly-bounded diodes (also referred to as “gateddiodes”) experience advantages over similar devices that use ShallowTrench Isolator (STI)-bounded diodes. For instance, in some ESDprotection applications, poly-bounded diodes provide a lower overshootvoltage and a faster rise time than similar devices with STI-boundeddiodes.

FIGS. 3 and 4 illustrate exemplary strip-type poly-bounded diodes, whichcan be incorporated into ESD protection devices. Various embodimentsinclude polygon-shaped, rather than strip-type, diodes. FIG. 5 is atop-down illustration of exemplary polygon-shaped poly-bounded diode500. Diode 500 is a P-type diode, and its cross-sectional view is thesame as that shown in FIG. 3A when cut along line A or B. For reference,poly structures 312 and 314 are shown. Perpendicular poly sections 512,514 are shown as well. While diode 300 (FIG. 3) is configured so thatthe various layers are laid out linearly along the longest dimension ofFIG. 3B, by contrast, the doped layers and poly structures of diode 500are arranged in a polygonal shape. Specifically, in diode 500, the dopedlayers and poly structures are laid out in a rectangle denoted by lengthand width dimensions L and W, respectively.

A poly-bounded diode with a polygonal layout structure, such as thatshown in FIG. 5, can reduce the overall device size for the same EDSlevel and also reduce parasitic capacitance, as compared to thestrip-type diodes of FIGS. 3 and 4. Equation 1 gives a formula forparasitic capacitance per ESD level, as it is affected by L and W.

$\begin{matrix}{\frac{Capacitance}{{ESD}\mspace{14mu}{Level}} = {\frac{{C_{j}({WL})} + {C_{jsw}\left( {{2W} + {2L}} \right)}}{{2W} + {2L}} = {{\frac{C_{j}}{2}\frac{WL}{W + L}} + C_{jsw}}}} & (1)\end{matrix}$Where C_(j)=junction capacitance

C_(jsw)=junction/sidewall capacitance

In Equation 1, C_(j) is the capacitance between the doped region down tothe well junction, and C_(jsw) is the capacitance between the regionsidewalls and the well junction. Well junctions and sidewalls arelabeled in FIGS. 3A and 4A. The specific dimensional relationship whereW=L provides the optimum capacitance/ESD level ratio for a rectangulardevice, though a given device may use a relationship other than W=L ifdesired.

The exemplary diode shown in FIG. 5 conforms to a rectangular shape, butthe scope of embodiments is not so limited. In fact, the scope ofembodiments includes diodes that have layers arranged according to anyarbitrary polygonal shape. FIG. 6 is an illustration of exemplaryembodiments including hexagonal poly-bounded diode 610 and octagonalpoly-bounded diode 650. Diodes 610 and 650 are both N-type diodes havingcross-section 670. It is understood that P-type diodes according tovarious embodiments may be made as well.

FIG. 7 is a flowchart of exemplary method 700 for fabricating a device,adapted according to one embodiment. The method 700 begins with block710 in which a plurality of poly-bounded doped regions are formed on asubstrate in the shape of a polygon. The doped regions and thepolysilicon structures can be formed in any suitable manner now known orlater developed, including by conventional deposition, etching, andimplantation methods. By contrast to the diode 400, which aslinearly-shaped poly layers, the devices of this example have a polylayer that is shaped as a closed polygon when viewed from the top down,such as is depicted in FIGS. 5 and 6.

The method 700 continues with block 720 in which input/output terminalsto the poly-bounded doped regions are formed to create a gated diode.The input/output terminals can include power terminals, signal inputs,and the like. In one example, the terminals communicate with an RF padon a circuit board for receiving and/or transmitting RF signals.

The method 700 continues at block 730, which includes disposing thegated diode in a circuit where the gated diode functions as an ESDprotection device. In one example, the circuit further includes RFcircuitry (e.g., a digital signal processor, low noise amplifier, or thelike) and a clamping device. The gated diode is placed between the powerand ground of the circuit and in parallel with the clamping device andthe RF circuitry. Some embodiments include using two or more gateddiodes that may be arranged, e.g., as shown by devices 110, 111 ofFIG. 1. During an ESD event, the gated diode and the clamping circuitprotect the RF circuitry from the harmful effects of the ESD event.

FIG. 8 shows one example circuit 800 in which polygonal gated diodes canbe used. Diodes 801, 802 are arranged with between Vdd and Vss, and oneor both of diodes 801, 802 are configured as polygonal gated diodes.Circuit 800 further includes RF circuitry (in this case, low noiseamplifier 803) and power clamp 804. FIG. 8 illustrates ESD current pulsepaths created by diodes 801, 802. PS is a positive ESD pulse, Vssgrounded. ND is a negative ESD pulse, Vdd grounded.

Returning to FIG. 7, method 700 can be used to fabricate diodes anddevices that use diodes, such as those given in examples above. Method700 is shown as a series of discrete actions, and it is understood thatvarious methods within the scope of embodiments may differ. Forinstance, other methods may add, omit, rearrange, or modify someactions.

Various embodiments provide one or more advantages over other designs.For instance, as mentioned above, poly-bounded diodes generally havelower overshoot voltages than do other kinds of diodes, such asSTI-bounded diodes. Thus, in some designs, poly-bounded diodes adaptedto the examples above and used as ESD protection devices may providereduced overshoot and, consequently, facilitate faster clamping.Additionally, some designs using polygonal, rather than strip-type,diodes may provide for lower parasitic capacitance and smaller devicesize for the same ESD protection level. For any of the embodimentsdisclosed herein, polygonal poly-bounded diodes can be used, asappropriate, in place of other kinds of diodes.

In some embodiments, the power clamp 804 (FIG. 8) is designed to providea low-impedance path between the power rails during an ESD event and is,therefore, designed to be relatively large. Such design may include anetwork of transistors, resistors, and a large bypass capacitor (notshown). However, a large power clamp may in some instances lead toincreased leakage current and chip area cost. The embodiment of FIG. 9addresses such issue by providing an ESD protection network with diodesand inductors to reduce current leakage and chip area cost.

FIG. 9 is an illustration of exemplary circuit 900 adapted according toone embodiment. Circuit 900 can be conceptually divided into two maincomponents—ESD protection network 920 and RF front end circuitry 940that includes a low noise amplifier and an impedance matching network.The present discussion will focus on ESD network 920 rather thandescribe RF front end circuitry 940. It is understood that the scope ofembodiments is not limited to applications that include any particulartypes of protected circuitry, as some other embodiments are adapted toprovide ESD protection to any of a variety of RF and millimeter wavedevices. In FIG. 9, the following abbreviations appear as subscripts tothe components: B=bias, INT=input top; D=drain; S=source;GS=gate-source; M=matching.

ESD network 920 includes an RF input (RFin), which communicates with RFfront end circuitry 940 through ESD network 920. Inductor 921 is placedbetween RFin and RF front end circuitry 940. Diode 923 is coupled to Vddand coupled to RFin through inductor 921. Diode 922 is coupled to RFinthrough inductor 921 and coupled to Vss through inductor Ls. ESDprotection network 920 also includes diode 925 and diode string 924.Diode string 924 is shown with three diodes in this embodiment, and itis understood that in other embodiments diode string 924 may includeone, two, or more diodes. Any of the diodes described in this embodimentmay be implemented as a string of two or more diodes, though only onediode string is shown in FIG. 9. In some examples, a string of diodes ischosen over a single diode to provide a voltage drop for a largeoperation voltage.

Furthermore, it should be noted that diode 922 is shown as part of ESDnetwork 920 but not as part of RF front end circuitry 940. Nevertheless,in the case of diode 922 the distinction is somewhat artificial, asdiode 922 serves as part of the matching network as well by providingcapacitance to the matching impedance.

In normal operation, diodes 921-925 are reversed biased and act ascapacitors. The extra capacitance can provide noise decoupling and aperfect AC ground. In many applications the capacitance provided bydiodes 922-925 takes the place of a large bypass capacitor. During anESD event, diodes 922-925 become forward biased and remove the ESDcurrent.

FIG. 10 is an illustration of circuit 900 showing the current pathsduring an ESD event when diodes 922-925 are forward biased. Thefollowing abbreviations apply to the current paths: PS=positive ESDpulse, Vss grounded; PD=positive pulse, Vdd grounded; NS=negative ESDpulse, Vss grounded; ND=negative ESD pulse, Vdd grounded. Diode string924 is shown as a power clamp in FIG. 10 because it provides a voltagedrop that clamps the ESD pulse. Diode 925 can also be considered a powerclamp in some embodiments because it provides a clamping voltage drop aswell.

Furthermore, in this embodiment, the width of the metal of inductor 921is at least five microns in order to handle current NS. Otherembodiments may use different configurations for inductor 921 so long asthose configurations are capable of safely and reliably conductingcurrent NS. The inductance value depends on the particular RF design ofcircuit 900. Also, the sizes of the individual diodes 922-925 isflexible from application to application and can be based on a number ofcircuit characteristics. Examples of circuit characteristic thatinfluence the sizes of diodes 922-925 include the capacitancerequirements of the circuit as a whole, desired voltage drop, andimpedance provided by a matching network.

FIG. 11 shows an alternate embodiment circuit 1100 with a slightlydifferent architecture than the embodiment shown in FIGS. 9 and 10.Circuit 1100 adds diode 1101 and moves diode 923 to connect to a nodebetween RFin and inductor 921. FIG. 11 shows the resulting current pathsduring an ESD event. Once again, diodes 924 and 925 clamp the ESD pulseby applying a voltage drop thereto. The addition of diode 1101 providesfor a more robust ESD protection network, especially for ND pulses, thanthat shown in FIGS. 9 and 10. Specifically, the addition of diode 1101provides an extra current path for ESD pulses. Some applications can beadapted for use with either circuit 900 or circuit 1100.

FIG. 12 is an illustration of exemplary method 1200 adapted according toone embodiment for fabricating a circuit. The method 1200 begins withblock 1210 in which an RF pad is placed in communication with RF frontend circuitry. In one example, block 1210 includes placing the RF padand the RF front end circuitry on a circuit board. In another example,block 1210 includes routing a connection from the RF pad to RF front endcircuitry within a package of dies. Various embodiments may use anytechniques now known or later developed to fabricate devices and toconnect the devices to make a working product.

Method 1200 continues with block 1220, which includes disposing a firstand a second diode in the circuit. The first and second diodes areconfigured to be in communication with the RF pad and the RF front endcircuitry, and they are placed so that their forward direction is fromVss to Vdd. While block 1220 refers to Vss and Vdd, it is understoodthat such terms are not meant to limit the scope of embodiments to NMOSdevices only. On the contrary, block 1220 encompasses any power andcomplementary power arrangement, such as V+/V− and power/ground asexamples.

In block 1230, an inductor is disposed in the circuit in communicationwith the first and second diodes and between the RF pad and the RF frontend circuitry. A first example is shown in FIG. 9, and a second exampleis shown in FIG. 11, where inductor 921 can be placed either closer tothe RF pad or closer to the RF front end circuitry. The first and seconddiodes are placed so that they are reverse biased during normaloperation and forward biased in the event of an ESD pulse.

Embodiments are not limited to the specific example shown in FIG. 12.Other embodiments may add, omit, rearrange, or modify one or moreactions. In one example, another diode is added between the RF pad andVss, as shown in FIG. 11. In another example, other diodes and/or diodestrings are placed between Vss and Vdd to provide additional ESD currentpaths and to provide voltage drops for clamping. Furthermore, any of thediodes in the example of method 1200 may be implemented as single diodesor as diode strings, as appropriate for a given application.

Some embodiments include one or more advantages. For instance, someembodiments avoid the use of a large bypass capacitor by the use ofreverse-biased diodes that provide capacitance during normal operation.Such embodiments may experience a savings in device size and cost.Furthermore, some embodiments may avoid the use of a large,transistor-based power clamp by using diodes or diode strings as powerclamps, thereby saving device size and cost.

The embodiments described above work well in many applications. However,some applications involving high data rate wireless communication of 15GHz or more may experience undesirably high parasitic capacitance ifused with some diode-based ESD protection devices. Accordingly variousembodiments herein provide an inductor-based ESD protection device thatcan be used as an alternative to some diode-based ESD protection devicesand can also be integrated with an impedance matching circuit.

FIG. 13 is an illustration of exemplary circuit 1300, adapted accordingto one embodiment. Circuit 1300 includes protected circuit 1303, whichis shown herein as a low noise amplifier as one example. In otherembodiments, a protected circuit can be any type of circuit that mightbenefit from ESD protection. Circuit 1300 also includes input matchingnetwork 1302, which has an ESD protection circuit, and power clamp 1301.As in previously-described examples, the ESD protection circuit directsan ESD current to power clamp 1301, and power clamp 1301 mitigates theESD current. The following figures provide more detail for severalembodiments of matching network 1302.

FIG. 14 is an illustration of exemplary matching circuit 1400, adaptedaccording to one embodiment. Circuit 1400 can be used as input matchingnetwork 1302 in FIG. 13, by coupling lump inductor 1401 to Vss andcoupling capacitor 1402 to protected circuit 1303 at M1. Matchingnetwork 1302 is designed to provide an appropriate input impedance,which is achieved by selection of inductor 1401 and capacitor 1402. Inthe present example, inductor 1401 is placed between the RF input (RFin)and Vss, thereby creating a path for ESD currents.

Some embodiments may use a bi-directional transmission line ESD inductor(not shown) coupling an RF input to Vss before a matching network. Suchembodiments use the transmission line ESD inductor as an open stubduring normal operation. However, the transmission line ESD inductor is¼ wavelength or longer in order to act as an open stub, which isrelatively large even at high frequencies. By contrast, otherembodiments such as that shown in FIG. 14 incorporate ESD protectioninto the matching network and use a matching inductor for ESDprotection. Inductor 1401 does not typically provide an open stub atnormal operating frequencies, but inductor 1401 does provide an ESDcurrent path during ESD events while providing impedance matching duringnormal operation. An advantage of the embodiment shown in FIG. 14 isthat inductor 1401 may be made shorter than ¼ wavelength of the inputsignal when inductor 1401 is embodied as a transmission line inductor(e.g., a meander inductor, a spiral inductor, or the like). The size ofinductor 1401 can be different from application to application, beinginfluenced primarily by the specific characteristics of the matchingimpedance. The amount of voltage overshoot that can be handled by agiven ESD protection device in this embodiment is chiefly influenced bythe width of the metal of the inductor.

It is understood that the protected circuit may have a normal operatingfrequency range rather than a single, discrete operating frequency.Accordingly, references to the normal operating frequency or normaloperating wavelength of the protected circuit include such ranges.

Similar inductor-based ESD protection circuits are not limited to theexample shown in FIG. 14. Other embodiments may include differentconfigurations, as shown in the next several figures.

For instance, FIG. 15 is an illustration of exemplary matching circuit1500, adapted according to one embodiment. Circuit 1500 includesinductor-based ESD protection using transformer 1501. Similar to theexample above in FIG. 14, circuit 1500 uses transformer 1501 forimpedance matching, and transformer 1501 is coupled to Vss therebyproviding an ESD bypass current path.

The embodiment of FIG. 14 can be modified in other ways as well. FIGS.16-19 provide four other examples of circuits that can be used ascircuit 1302 (FIG. 13), and it is understood that the number ofdifferent possible designs is not limited to those specifically shownherein. Selection of a design may take into consideration factors suchas the specific input impedance that should be achieved for a givenapplication. Each of the designs shown in FIGS. 16-19 can be used toprovide a different input impedance.

FIG. 16 is an illustration of exemplary matching circuit 1600, adaptedaccording to one embodiment. When compared with the embodiment of FIG.14, circuit 1600 adds inductor 1601 in series with capacitor 1402between capacitor 1402 and the protected circuit (not shown).

FIG. 17 is an illustration of exemplary matching circuit 1700, adaptedaccording to one embodiment. Circuit 1700 adds inductor 1701 in serieswith capacitor 1402 between capacitor 1402 and RFin.

FIG. 18 is an illustration of exemplary matching circuit 1800, adaptedaccording to one embodiment. Circuit 1800 adds capacitor 1801 betweenthe signal line and Vss after capacitor 1402. Inductor 1401 andcapacitor 1801 are coupled to opposite terminals of capacitor 1402.

FIG. 19 is an illustration of exemplary matching circuit 1900, adaptedaccording to one embodiment. Circuit 1900 adds inductor 1901 between thesignal line and Vss after capacitor 1402. Inductor 1401 and inductor1901 are coupled to opposite terminals of capacitor 1402.

FIGS. 20 and 21 provide variations on the embodiment shown in FIG. 15,where a transformer is used for impedance matching and ESD currentbypass. Specifically, FIG. 20 adds inductor 2001 in series withcapacitor 1402 between capacitor 1402 and the protected circuit (notshown). FIG. 21 adds inductor 2101 in series with capacitor 1402 betweencapacitor 1402 and transformer 1501.

FIG. 22 is an illustration of exemplary method 2200 for fabricating adevice according to one embodiment. In block 2210, a protected device isfabricated. In some embodiments the protected device is fabricated on acircuit board or as a stand-alone device. In other embodiments, theprotected device is fabricated on a semiconductor chip and is connectedto other components within the semiconductor chip and/or outside of thesemiconductor chip. The protected device can include any electronicdevice, though a specific example includes RF front end circuitry.

In block 2220, an ESD protection device is fabricated between a signalinput terminal and the protected device. Fabricating the ESD protectiondevice may include, e.g., disposing a first inductor between the signalinput terminal and Vss. The first inductor has a length less than ¼wavelength.

Fabricating the ESD protection device may also include disposing a firstcapacitor between the signal input terminal and the protected device. Inthis embodiment, the ESD protection device is part of the core design ofthe circuit and is included in the matching network.

The scope of embodiments is not limited to the specific example ofmethod 2200. For instance, other embodiments may include adding orrearranging components, as shown in FIGS. 15-21.

Various embodiments may provide advantages over other techniques. Forinstance, compared to some diode-based ESD protection schemes that use alarge bypass capacitor, the embodiments of FIGS. 13-22 have theadvantages of bi-directional operation, a lower on-resistance state, anda lower voltage drop during an ESD event.

Compared to embodiments using Silicon Controlled Rectifiers (SCRs), theembodiments of FIGS. 13-22 have the advantages of lower parasiticcapacitance, higher ESD turn-on speed, and much easier RF modelingproperties. Compared to embodiments using a transmission line inductoras an open stub, the embodiments of FIGS. 13-22 have the advantages of asmaller area size, lower loss, and flexible practical design and layoutrouting because the embodiments of FIGS. 13-22 can use smallerinductors.

It is understood for each of the embodiments shown above, additionalprocesses may be performed to complete the fabrication of the ESDprotection device. For example, these additional processes may includedeposition of passivation layers, formation of contacts, and formationof interconnect structures (e.g., lines and vias, metal layers, andinterlayer dielectric that provide electrical interconnection to thedevice). Other additional processes may include, e.g., PCB fabricationprocesses and semiconductor die packaging processes. For the sake ofsimplicity, these additional processes are not described herein.

The foregoing has outlined features of several embodiments so that thoseskilled in the art may better understand the detailed description thatfollows. Those skilled in the art should appreciate that they mayreadily use the present disclosure as a basis for designing or modifyingother processes and structures for carrying out the same purposes and/orachieving the same advantages of the embodiments introduced herein.Those skilled in the art should also realize that such equivalentconstructions do not depart from the spirit and scope of the presentdisclosure, and that they may make various changes, substitutions andalterations herein without departing from the spirit and scope of thepresent disclosure. For example, embodiments shown as NMOS devices canbe extended to PMOS devices with a similar structure and configurationexcept that all doping types may be reversed and dimensions are modifiedaccording to PMOS design. Further, the PMOS device may be disposed in adeep n-well pocket for isolating the device.

What is claimed is:
 1. A circuit comprising: a Radio Frequency (RF)input; a first inductor connected in series between the RF input and RFfront end circuitry; a first diode connected to the RF input and to thefirst inductor and to a power line; and a second diode connected to theRF input and to the first inductor and to a complementary power line,the second diode connected to the complementary power line through asecond inductor and connected to a node between the first inductor andthe RF front end circuitry, in which the first and second diodes arereverse biased during normal operation of the RF front end circuitry,and in which the first and second diodes provide respective first andsecond electrostatic discharge (ESD) current paths away from the RFfront-end circuitry during an ESD event, in which the first diodeprovides the first ESD current path from the RF input to the power line,and wherein the second diode provides the second ESD current path fromthe complementary power line through the second inductor to the RFinput.
 2. The circuit of claim 1 in which the RF front end circuitrycomprises a Low Noise Amplifier (LNA).
 3. The circuit of claim 1 inwhich the first inductor is placed between a node connecting the firstand second diodes and the RF input.
 4. The circuit of claim 1, furthercomprising: a diode string coupled to the power line and complementarypower line and with a forward direction opposite that of the first andsecond diodes; and a third diode in parallel with the diode string andwith a forward direction the same as that of the first and seconddiodes.
 5. The circuit of claim 4 in which the diode string comprises asingle diode.
 6. The circuit of claim 4 wherein the diode stringcomprises a plurality of diodes.
 7. The circuit of claim 1 in which thefirst inductor is greater than five microns wide.
 8. A circuitcomprising: a Radio Frequency (RF) input coupled to RF front endcircuitry; a first inductor connected in series between the RF input andthe RF front end circuitry; and a first diode and a second diode betweenthe RF input and the RF front end circuitry, the first diode arranged toprovide a first electrostatic discharge (ESD) current path between theRF input and a power line, the second diode arranged to provide a secondESD current path between the RF input and a complementary power line,the second diode connected to the complementary power line through asecond inductor and connected to a node between the first inductor andthe RF front end circuitry.
 9. The circuit of claim 8 in which RF frontend circuitry comprises at least one of a Low Noise Amplifier (LNA) andan impedance matching network.
 10. The circuit of claim 8 in which thefirst inductor is placed between a node connecting the first and seconddiodes and the RF input, the circuit further comprising a third diodeproviding an ESD current path between the RF input and the complementarypower line.
 11. The circuit of claim 8, further comprising: a diodestring in parallel to the first and second diodes and with a forwarddirection opposite that of the first and second diodes; and; a thirddiode in parallel with the first and second diodes and with a forwarddirection the same as that of the first and second diodes.
 12. Thecircuit of claim 11 in which the diode string comprises a single diode.13. The circuit of claim 11 in which the diode string comprises aplurality of diodes.
 14. The circuit of claim 8 in which the firstinductor is greater than five microns wide.
 15. A method of fabricatinga circuit, the method comprising: connecting a Radio Frequency (RF)input with RF front end circuitry; disposing a first and a second diodein the circuit so that the first and second diodes are connected to theRF input and the RF front end circuitry, the first and second diodesboth arranged with a forward direction from a complementary power lineto a power line; and disposing a first inductor in the circuit so thatthe first inductor is connected to the first and second diodes and is inseries between the RF input and the RF front end circuitry, wherein thesecond diode is connected to a node between the first inductor and theRF front end circuitry; disposing a second inductor in the circuitbetween the second diode and the complementary power line.
 16. Themethod of claim 15, further comprising: disposing a diode string in thecircuit in parallel to the first and second diodes and with a forwarddirection opposite that of the first and second diodes; and disposing athird diode in the circuit in parallel to the first and second diodesand with a forward direction the same as that of the first and seconddiodes.
 17. The method of claim 15, further comprising: coupling a thirddiode to the first diode so that the third diode has a forward directionfrom the complementary power line to the power line in which theinductor is placed between the first and second diodes and between theRF input and the second diode.